 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 512K x 8 SRAM MODULE SYS8512FKX-70/85/10/12 Issue 5.0: November 1999 Description The SYS8512FKX is plastic 4M Static RAM Module housed in a standard 32 pin Dual-In-Line package organised as 512K x 8. The module utilises fast SRAMs housed in TSOP packages, and uses double sided surface mount techniques, buried decoder and dual board construction to achieve a very high density module. The module has Chip Select, Write Enable and Output Enable control inputs; the Output Enable pin allows faster access times than address access during a Read Cycle. Features * * * * * Access Times of 70/85/100/120 ns. Low seated height 32 Pin 0.6" Dual-In-Line package with JEDEC compatible pinout. 5 Volt Supply 10%. Low Power Dissipation: Average (min cycle) 605mW (maximum). Standby (CMOS) 44mW (maximum). Completely Static Operation. Equal Access and Cycle Times. All Inputs and Outputs Directly TTL Compatible. On-board Supply Decoupling Capacitors. * * * * Block Diagram AO - A 16 D0 - D7 WE Pin Definition A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS D7 D6 D5 D4 D3 OE 128K x 8 SRAM CS 128K x 8 SRAM CS 128K x 8 SRAM CS 128K x 8 SRAM CS DECODER Pin Functions A17 CS A18 Address Inputs Data Input/Output Chip Select Input Read/Write Input Output Enable Input Power (+5V) Ground PACKAGE TOP VIEW A0 - A18 D0 - D7 CS WE OE VCC GND ISSUE 5.0 November 1999 SYS8512FKX-70/85/10/12 DC OPERATING CONDITIONS Absolute Maximum Ratings (1) Parameter Voltage on any pin relative to VSS Power Dissipation Storage Temperature Notes : Symbol VT PT TSTG min -0.3V -55 typ 1 - max +7 +150 unit V W o C (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (2) Vt can be -3.5V pulse of less than 20ns. Recommended Operating Conditions Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temperature Symbol VCC VIH VIL TA TAI min 4.5 2.2 -0.3 0 -40 typ 5.0 - max 5.5 Vcc + 0.3 0.8 70 85 unit V V V o o C C (I) DC Electrical Characteristics (VCC=5V10%) TA 0 to 70OC min - Parameter Symbol Test Condition ILI1 ILO I CC TTL levels CMOS levels 0V - VIN - VCC CS = VIH, VI/O = GND to VCC CS = VIL ,II/O = 0mA, VIL - VIN - VCC-2.1V typ(2) max Unit 16 70 24 5 0.2 10 8 8 45 110 40 12 8 500 A A mA mA mA mA mA A I/P Leakage Current A0~A16, OE Output Leakage Current D0~D7 Operating Supply Current Average Supply Current I CC1 Min. Cycle, CS = VIL, VIN = VIL/VCC-2.1V I CC2 Min. Cycle, CS - 0.2V, VIN = 0.2V/VCC-0.2V ISB ISB1 ISB2 CS,A17-A18 = VCC-2.1V, VIL - VIN - VCC-2.1V CS,A17-A18 = VCC-0.2V, 0.2 - VIN - VCC-0.2V As above Standby Supply Current TTL levels CMOS levels -L Part Output Voltage VOL IOL = 2.1mA VOH IOH = -1.0mA 2.4 - 0.4 - V V Typical values are at VCC=5.0V,TA=25oC and specified loading. 2 SYS8512FKX-70/85/10/12 ISSUE 5.0 November 1999 Capacitance (VCC=5V10%,TA=25oC) Note: Capacitance calculated, not measured. Parameter Input Capacitance (CS, A17, A18) I/P Capacitance (other) I/O Capacitance Operation Truth Table Symbol CIN1 CIN2 CI/O Test Condition VIN = 0V VIN = 0V VI/O = 0V max 10 40 40 Unit pF pF pF CS H L L L OE X L L H WE X H L L DATA PINS High Impedance Data Out Data In Data In SUPPLY CURRENT ISB1 , ISB2 ICC1 , ICC2 ICC1 , ICC2 ICC1 , ICC2 MODE Standby Read Write Write Notes : H = VIH : L =VIL : X = VIH or VIL Low Vcc Data Retention Characteristics - L Version Only -L Part Parameter VCC for Data Retention Data Retention Current Symbol Test Condition VDR CS - VCC-0.2V VCC = 3.0V, CS = VCC-0.2V min typ(1) 2.0 - max - I CCDR2 I CCDR3 Chip Deselect to Data Retention Time Operation Recovery Time t CDR tR TOP = 0C to 70C TOP = TAI - 9 - 230 310 A A - See Retention Waveform See Retention Waveform 0 5 - - 0 0 - - ns ms Notes (1) Typical figures are measured at 25C. (2) This parameter is guaranteed not tested. AC Test Conditions * Input pulse levels: 0V to 3.0V * Input rise and fall times: 5ns * Input and Output timing reference levels: 1.5V * Output load: see diagram * VCC=5V10% Output Load 3 ISSUE 5.0 November 1999 SYS8512FKX-70/85/10/12 AC OPERATING CONDITIONS Read Cycle -70 Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Output Hold from Address Change Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to O/P in High Z -85 min 85 10 10 5 0 0 -10 max 85 85 55 30 30 -12 max - Symbol min t RC tAA tACS tOE t OH tCLZ tOLZ t CHZ 70 10 10 5 0 0 max 70 70 50 25 25 min 100 10 10 5 0 0 min 120 10 10 5 0 0 max Unit 120 120 70 45 45 ns ns ns ns ns ns ns ns ns 100 100 60 35 35 Output Disable to Output in High Z t OHZ Notes. (1) tHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels.These parameters are sampled and not 100% tested. Write Cycle -70 Parameter Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output active from end of write -85 min 85 80 80 0 65 5 0 35 0 5 -10 max 30 - -12 max 35 - Sym t WC t CW t AW tAS t WP t WR tWHZ t DW t DH tOW (10) (11) min 70 60 60 0 55 5 0 30 0 5 max 25 - min 100 90 90 0 75 10 0 40 0 5 min 120 100 100 0 85 10 0 45 0 5 max Unit 40 ns ns ns ns ns ns ns ns ns ns 4 SYS8512FKX-70/85/10/12 ISSUE 5.0 November 1999 Read Cycle Timing Waveform (1,2) t RC Address t AA OE t OE t OH t OLZ t ACS t CLZ t OHZ Don't care. CS Dout Data Valid t CHZ Notes (1) WE is High for Read Cycle. (2) tHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels.These parameters are sampled and not 100% tested. Write Cycle No.1 Timing Waveform tWC Address t WR (4) OE t AS (3) t AW t CW (2) (6) CS Don't Care WE t OHZ (5) t WP (1) High-Z tDW tDH tOW Dout High-Z Din 5 ISSUE 5.0 November 1999 SYS8512FKX-70/85/10/12 Write Cycle No.2 Timing Waveform tWC Address t AS (3) t CW (2) t WR (4) CS t AW tWP (1) WE tWHZ(5) t OW High-Z t DW tOH (7) (8) Don't Care Dout High-Z t DH Din AC Characteristics Notes (1) A write occurs during the overlap (tWP) of a low CS and a low WE. (2) tCW is measured from the earlier of CS or WE going high to the end of write cycle. (3) tAS is measured from the address valid to the beginning of write. (4) tWR is measured from the earliest of CS or WE going high to the end of write. (5) During this period, I/O pins are in the output state. Input signals out of phase must not be applied. (6) If CS goes low simultaneously with WE going low or after WE going low , outputs remain in a high impedance state. (7) DOUT is in the same phase as written data of this write cycle. (8) DOUT is the read data of next address. (9) If CS is low during this period, I/O pins are in the output state, and inputs out of phase must not be applied to I/O pins. (10) This parameter is sampled and not 100% tested. (11) tWHZ is defined as the time at which the outputs achieve open circuit conditions and is not referenced to output voltage levels. This parameter is sampled and not 100% tested. Data Retention Waveform Vcc DATA RETENTION MODE 4.5V 4.5V t CDR 2.2V tR 2.2V V DR CS > Vcc -0.2V 0V CS 6 SYS8512FKX-70/85/10/12 ISSUE 5.0 November 1999 Package Information 42.50 max. 15.92 max. 6.0 max. 3.50 +/-0.50 2.54 typ. min. 15.24 typ. Dimensions in mm Ordering Information SYS8512FKXLI-10 Speed 70 85 10 12 = 70 ns = 85 ns = 100 ns = 120 ns Temperature Range Blank = Commercial Temperature I = Industrial Temperature Blank = Standard Part L = Low Power Part Power Consumption Package Organization Memory Type FKX = Plastic 32 pin DIL 8512 = 512K x 8 SYS = Static RAM Although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantability or fitness for a particular purpose. Our Products are subject to a constant process of development. Data may be changed at any time without notice. Products are not authorised for use as critical components in life support devices without the express approval of a company director. 7 |
Price & Availability of SYS8512FKX-85
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |